Anwendungsmodellierung und -abbildung auf Multiprozessor-System-on-Chip-Plattformen
Zusammenfassung der Projektergebnisse
The amount of embedded systems which are composed by multiple interconnected processing elements (PE) is currently increasing, mainly because of two distinct facts: first, the need for spatial distribution of the subsystems in order to cope with the requirements of ubiquitous computing; and second, the limits of CMOS scaling, which also limit how fast integrated circuits can operate and thus require increased PE parallelism as a compensation in order to deliver the performance improvements expected by the electronic systems market. As the current trend for both facts is unlikely to change anytime soon, it is expected that communication-centric multiprocessor embedded systems will be even more common in the near future. While plenty of research was done in the last decades on general-purpose multiprocessing system (such as symmetric multiprocessor systems and clusters), there is still a lack of languages, methods and techniques supporting the specification, design and optimization of multiprocessor systems that are targeted specifically to a given application (or family of applications). Furthermore, a programming model that would allow developers to deal with the system as a whole (instead of dealing with each processing element individually) is still mostly an open question. In order to address these questions, this project delivers a framework supporting the specification and design of application-specific systems based on multiple interconnected processing elements. The framework is based on the joint application of actor-orientation and type systems (materialized through the use of UML sequence diagrams). While taking advantage of state-of-the-art techniques, the project goal is to produce a designer-centric approach that can be easily extended and eventually adopted by industry in a short time frame. A basic programming model is proposed, based on behavioral patterns, and is used within the delivered framework to allow the validation of different system properties under realistic application-specific scenarios. Specific application scenarios are created as early as possible in the design process as a set of actors executing concurrently, thus allowing developers to analyze their ideas before they have to commit to a specific processor architecture or hardware implementation. Actors can use different models of computation, hence taking advantage of a flexible model that can address in a unique framework a large set of applications. To show the applicability and the versatility of the proposed approach, the project is applied to the proposed programming model on the design of a system composed of multiple processing elements interconnected through a packet switched network-on-chip. The programming model, together with its modeling and execution framework, supports the analysis of properties which are most relevant to embedded systems like the impact of using heterogeneous PEs on the overall system performance. A monitoring system feeds back information about the current network traffic to intelligent algorithms that map tasks to their optimum position on the platform.
Projektbezogene Publikationen (Auswahl)
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“Characterising Embedded Applications Using a UML Profile,” in International Symposium on Systemon-Chip (ISSOC), 2009, pp. 172-175
S. Määttä, L.S. Indrusiak, L.C. Ost, L.H. Möller, M. Glesner, F.G. Moraes, and J. Nurmi
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“NoCScope: A Graphical Interface to Improve Networks-on-Chip Monitoring and Design Space Exploration,” in International Design and Test Workshop (IDT), 2009, pp. 1-6
L.H. Möller, L.S. Indrusiak, and M. Glesner
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“A Case Study of Hierarchically Heterogeneous Application Modelling Using UML and Ptolemy II,” in International Symposium on System-on-Chip (ISSOC), 2010, p. 68–71
S. Määttä, L.S. Indrusiak, L.C. Ost, L.H. Möller, M. Glesner, F.G. Moraes, and J. Nurmi
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“Evaluating the Impact of Communication Latency on Applications Running over On-Chip Multiprocessing Platforms: A Layered Approach,” in International Conference on Industrial Informatics (INDIN), 2010, p. 148–153
L.S. Indrusiak, L.C. Ost, F.G. Moraes, S. Määttä, J. Nurmi, L.H. Möller, and M. Glesner
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“Graphical Interface for Debugging RTL Networks-on-Chip,” in Biennial Baltic Electronics Conference (BEC), 2010, p. 181–184
L.H. Möller, H.V. Jesus, F.G. Moraes, L.S. Indrusiak, T. Hollstein, and M. Glesner
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“Improving QoS of Multi-Layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers,” in International Conference on Field Programmable Logic and Applications (FPL), 2010, p. 229–233
L.H. Möller, P. Fischer, F.G. Moraes, L.S. Indrusiak, and M. Glesner
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“Instruction Set Simulator for MPSoCs based on NoCs and MIPS Processors,” in International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2010, pp. 7-12
L.H. Möller, A. Rodrigues, F.G. Moraes, L.S. Indrusiak, and M. Glesner
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“Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms,” International Journal of Embedded and Real-Time Communication Systems (IJERTCS), vol. 1(1), 2010, pp. 86-101
S. Määttä, L.H. Möller, L.S. Indrusiak, L.C. Ost, F.G. Moraes, J. Nurmi, and M. Glesner
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“Development of a Heterogeneous Multiprocessor Systems‐on‐chip on an Actor‐Oriented Platform,” Master Thesis, Darmstadt University of Technology, 2011, 54 p.
Muhammad Faraz Ishrat
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“Exploring Dynamic Mapping Impact on NoC-based MPSoCs Performance Using a Model-based Framework,” in Symposium on Integrated Circuits and Systems Design (SBCCI), 2011, p. 6
L.C. Ost, M. Mandelli, G.M. Almeida, L.S. Indrusiak, L.H. Möller, M. Glesner, G. Sassatelli, M. Robert, and F.G. Moraes
