Steigerung der Leistung von MOS-Bauelementen durch Stoßionisation
Zusammenfassung der Projektergebnisse
The lateral impact ionization MOSFET, which was developed to overcome the limit of 60 mV/dec for the sub-threshold swing of conventional MOSFETs, has the drawback of a high supply voltage and rapid degradation due to hot carriers. The vertical IMOS has been demonstrated to be able to overcome these limitations of the lateral IMOS. However, it is slow and has a remarkable hysteresis. In this project, a 2D device simulator including an II model for calculating the II rate of relaxed Si, strained Si and strained SiGe has been developed to investigate and optimize this device. Qualitative agreement between the simulations and experimental data for relaxed-Si IMOS was obtained. Through the simulations, the vertical IMOS has been optimized by the means of dimension scaling and strain engineering. It was found that a very thin floating body, e.g. 50nm, could help to improve the performance of the IMOS including a better I on /I off ratio, a reduced hysteresis and a much faster switching speed. The simulation results showed that it is possible to improve the characteristic of the vertical IMOS transistor with a strained SiGe layer. But the position of this layer inside the device must be chosen very carefully since such a layer can have various consequences. The avalanche multiplication factor is not increased by strained SiGe, therefore a layer inside the drain region has little influence. However, if the layer is incorporated in the p-body, it reduces the threshold of the turn-on of the IMOS. Experimental investigations of SSiGe-IMOS transistors might be guided by these simulation results. Finally, the noise performance for the vertical IMOS has been investigated. Although this noise is smaller than that in the lateral IMOS, it is still more than two orders of magnitude larger than its counterpart in the case without II. This fact might limit the application of the IMOS.
Projektbezogene Publikationen (Auswahl)
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“Comparison of (001), (110) and (111) Uniaxial- and Biaxial- Strained-Ge and Strained-Si PMOS DGFETs for All Channel Orientations: Mobility Enhancement, Drive Cirrent, Delay and Off-state Leakage”, International Electron Devices Meeting (IEDM), USA, December 2008
T. Krishnamohan, D. Kim, T. V. Dinh, A. T. Pham, B. Meinerzhagen, C. Jungemann, K. Saraswat
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“Impact ionization rates for strained Si and SiGe”, Solid-State Electronics, Vol. 53, pp. 1318-1324, 2009
T. V. Dinh, C. Jungemann
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“Impact ionization rates for strained SiGe”, The 10th International Conference on Ultimate Integration of Silicon (ULIS), pp. 77-80, Aachen, Germany, March 2009
T. V. Dinh, C. Jungemann
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“Investigation of the performance of strained-SiGe vertical IMOS-transistors”, The 39th European Solid-State Device Research Conf. (ESSDERC), pp. 165- 168, Athens, Greece, September 2009
T. V. Dinh, R. Kraus, C. Jungemann
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“Investigation of the Vertical IMOS-Transistor by Device Simulation”, The 10th International Conference on Ultimate Integration of Silicon (ULIS), pp. 281-284, Aachen, Germany, March 2009
R. Kraus, C. Jungemann
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“Analysis of the IMOS Transistor with a Floating Body”. Bundeswehr University, Neubiberg, Germany, 2010
R. Kraus, C. Jungemann
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“Full-Band Monte Carlo Simulations for Vertical Impact Ionization MOSFETs”. Ph.D. thesis, Bundeswehr University, Neubiberg, Germany, 2010
T. V. Dinh
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“Improving the high frequency performance of SiGe HBTs by a global additional uniaxial stress”, The 5th International SiGe Technology and Device Meeting (ISTDM), Stockholm, Sweden, May 2010
T. V. Dinh, S.-M. Hong, C. Jungemann
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“Investigation of the performance of strained-SiGe vertical IMOS-transistors”, Solid-State Electronics, Vol. 54, pp. 942-949, 2010
T. V. Dinh, R. Kraus, C. Jungemann
