Ensuring Robustness in Low-Power Asynchronous Circuits - ENROL

• Applicant: Professor Dr.-Ing. Milos Krstic
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: from 2018 to 2022
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 389059471

Currently, virtually all reasonably complex digital circuits, such as microprocessors, have all their internal operational sequences controlled by a rigid clock, i.e. these circuits operate synchronous. An alternative design paradigm, namely asynchronous design, when suitably optimized, offers the potential for realizing the same functionality with higher energy efficiency, higher performance and higher robustness. The project ENROL is dedicated to the latter aspect, namely the question how far asynchronous designs are indeed more robust than synchronous ones, in terms of being more tolerant to external interferences or sub-optimal operating conditions. To this end, in a first step a formal model shall be elaborated for the fault-free behavior of asynchronous circuits designed following the most relevant existing asynchronous approaches. In a next step all possible fault effects shall be expressed in that model, classified and associated with their respective probabilities. For those faults that turn out to be finally tolerated, the mechanisms underlying this tolerance shall be explored. The results thus obtained shall be compared with those for comparable synchronous circuits to give evidence for the hypothesized higher robustness of asynchronous circuits; the differences shall be quantified by means of suitable metrics. In this process, theoretical considerations will be accompanied by comprehensive simulation studies and experimental measurements for circuits whose design is part of the project as well.Based on the thorough understanding of the fault effects and the inherent fault tolerance mechanisms, well directed modifications to and extensions of the asynchronous circuits and concepts can be devised to further enhance their robustness. Here, the available concepts range from technological enhancements (transistor geometry and placement) over changes in the circuit towards coding methods. While fault-tolerance approaches for asynchronous designs do exist in the literature already, the systematic treatment of the topic from modelling to experiment, covering all relevant design asynchronous design paradigms, and directly comparing all alternatives, clearly represents a contribution to the state of the art.The results of ENROL will allow to give evidence for and to better leverage the robustness benefits of asynchronous design. This could make the latter more attractive for critical applications where designers would as well appreciate the other advantages like energy efficiency or higher performance. So on the long run ENROL will contribute to constructing fast and energy-efficient computers that yet work reliable under faults and sub-optimal conditions.

• DFG Programme: Research Grants
• International Connection: Austria
• Partner Organisation: Fonds zur Förderung der wissenschaftlichen Forschung (FWF)
• Co-Investigator: Professor Dr. Andreas Steininger