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Projekt Druckansicht

Untersuchung von GALS (Global Asynchronous Local Synchronous) Methoden zur Reduktion von Substrat Rauschen in BiCMOS Technologien-GASEBO

Fachliche Zuordnung Elektronische Halbleiter, Bauelemente und Schaltungen, Integrierte Systeme, Sensorik, Theoretische Elektrotechnik
Förderung Förderung von 2013 bis 2019
Projektkennung Deutsche Forschungsgemeinschaft (DFG) - Projektnummer 242241487
 
Erstellungsjahr 2020

Zusammenfassung der Projektergebnisse

The main goal of this project was to investigate the possibility of using GALS as a low-noise design approach for substrate noise reduction in mixed-signal integrated circuits in BiCMOS technologies, i.e. in lightly doped substrates. In order to be able to analyze GALS-based methodologies for substrate noise reduction in lightly doped substrates, the connection between the simultaneous switching activity and the generated substrate noise in such substrates was analyzed, and a simplified numerical model describing substrate noise propagation was developed. The plesiochronous GALS frequency scheme was chosen as the most suitable for substrate noise reduction. Two substrate noise reduction methodologies were developed: Harmonic-balanced plesiochronous GALS partitioning methodology, applicable for systems where on-chip parasitics are negligible compared to package parasitics. Theoretically it can provide a spectral peak attenuation of 20log(𝑀), and it enables targeting also higher harmonics for substrate noise reduction. The method can also be combined with power-balanced plesiochronous GALS partitioning. - Harmonic/area based or power/area based plesiochronous GALS partitioning methodology with power domain separation, applicable for systems where power domain separation is possible. This method also takes floorplanning into account. Achievable spectral peak attenuation depends on the number of supply/ground package pins, on substrate resistivity and chip dimensions. Both methodologies were theoretically analyzed, and for both of them an optimization algorithm was developed and numerically evaluated in MATLAB. For harmonic balanced plesiochronous GALS partitioning methodology, the algorithm was also embedded in EMIAS noise analysis tool, and tested on a real design example in this tool. The corresponding test chips have been designed in the project and the tests will be finalized soon. As a consequence of the GASEBO project the methodology for low-noise GALS partitioning has been introduced, which could be also utilized in the relevant application circuits. As a consequence, we could estimate the results as very positive and GASEBO project as successful.

Projektbezogene Publikationen (Auswahl)

 
 

Zusatzinformationen

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