Reliability Monitoring and Manging Built-In- Self Test (RM-BIST)
Zusammenfassung der Projektergebnisse
Reliability becomes one of the major concerns with VLSI scaling. The growing susceptibility of VLSI circuits to the environmental and external disturbances, process variations, radiation induced errors and aging factors requires reliability monitoring and managing approaches and Design-for-Reliability (DfR) built-in infrastructures for current and future technology nodes. The RM-BIST project tackled system reliability management and improvement, and characterized the mechanisms of circuit degradations. Methods for reliability monitoring and prediction are developed as well as structures and working procedures of Design-for-Reliability infrastructure. The central objectives of RM-BIST were Reusing existing DFT infrastructure for reliability screening and mitigation during runtime. Providing accurate prediction for short-term and long-term failure mechanisms, both at design time and on-line. Predicting critical system stats early to prevent failures by guiding on-line adaptation techniques. Improving system reliability using BIST-generated healing patterns and multiobjective load scheduling. The goals were reached by close cooperation of the two working groups in Stuttgart and Karlsruhe. First, methods for redesigning test structures have been developed. To efficiently access the integrated reliability monitors and other embedded instruments, reconfigurable scan networks (RSN) standardized as IEEE Std 1687 provide a cost-effective, flexible and scalable possibility. In the project, the first time a formal modeling method based on temporal abstraction has been developed. The model considers structural and functional dependencies of the RSN architecture and enables efficient formal verification of complex scan networks, as well as automatic generation of access patterns with optimal access time. The accessibility of embedded instrumentation offered by RSNs poses a serious security threat. To protect circuit against unauthorized access, this security problem has been addressed by two scalable fine-grained solutions for multi-level access management in RSNs. The second work package dealt with critical state identification, where Representative Critical Gates (RCGs) were selected, the workload of which correlates with the system critical state. For on-line prediction, an aging rate model is constructed, building the relation between the workload of the RCGs and the delay degradation rate of the circuit. An optimal number and placement of stability checkers was determined based on the sensitization possibility and topological distribution of the critical paths. By inserting the delay monitors at meticulously selected positions (observation points) in the circuit nets, the measurement latency of delay degradation and monitoring overhead are reduced simultaneously. Novel proactive workload monitors with only minimal implementation consumption enable early prediction of reliability issues and adoption of relevant proactive countermeasures. In a running system, the stress experienced by the RCGs are continuously observed by workload monitors and aggregated over a short period of time. Together with the averaged temperature, the averaged stress of RCGs is periodically fed to the aging rate prediction model evaluated in software, ideally during the idle time of any available processing unit. To improve the system reliability, a unified bit-flipping scan architecture was developed, facilitating fault tolerance as well as offline test by combining a checksum of the sequential state with the ability to flip arbitrary bits.
Projektbezogene Publikationen (Auswahl)
- Access Port Protection for Reconfigurable Scan Networks, Journal of Electronic Testing: Theory and Applications (JETTA) Vol. 30(6), 5 December 2014, pp. 711-723 (Best Paper Award of the year 2014)
R. Baranowski, M.A. Kochte and H.-J. Wunderlich
(Siehe online unter https://doi.org/10.1007/s10836-014-5484-2) - Bit-Flipping Scan - A Unified Architecture for Fault Tolerance and Offline Test, Proc. Design, Automation and Test in Europe (DATE), Dresden, Germany , Mar 24-28 2014
M.E. Imhof and H.-J. Wunderlich
- "Fine-Grained Aging Prediction Based on the Monitoring of Run-Time Stress Using DfT Infrastructure", in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2015, USA
A. Koneru, A. Vijayan, K. Chakrabarty, M. B. Tahoori
- "On-chip Droop-induced Circuit Delay Prediction Based on Support-Vector Machines", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2015
F. Firouzi, Y. Yang, K. Chakrabarty, and M.B. Tahoori
(Siehe online unter https://doi.org/10.1109/TCAD.2015.2474392) - Fine-Grained Access Management in Reconfigurable Scan Networks, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 2015
R. Baranowski, M.A. Kochte and H.-J. Wunderlich
(Siehe online unter https://doi.org/10.1109/TCAD.2015.2391266) - On-Line Prediction of NBTI-induced Aging Rates, Proc. of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE), Grenoble, France, 9-13 March 2015, pp. 589-592
R. Baranowski, F. Firouzi, F. Kiamehr, C. Liu, M. Tahoori and H.-J. Wunderlich
