Fully Integrated Optoelectronic Receiver with Robust PAM-N Data Recovery (FIORD)

• Applicants: Professor Dr.-Ing. Friedel Gerfers; Dr.-Ing. Andrea Malignaggi
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: since 2023
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 527822112

State-of-the-art silicon photonic transceivers use signal processing at both transmitter and receiver sides mostly performed using off-chip digital signal processors (DSPs). These solutions suffer from communication speeds up to 64 Gbaud, as these are severely limited by interconnect technologies such as bond wires. Next generation opto-electronic systems require at least 2-4x higher data rates per singe wavelength and lane, making such interconnect a fundamental bottleneck for opto-electronic transceivers towards 1-Tbps.The first key innovation of the proposed architectural solution to enable such transmission rates is the adoption of a fully monolithic implementation, where both optical components and electronic Rx and Tx circuits, including the critical clock and data recovery (CDR) together with the required first level digital signal processing units, are embedded on the same silicon substrate. Additional architectural innovations of the monolithically integrated clock and data recovery (CDR) together with a low-phase noise PLL, ensures wideband dynamic phase and frequency tracking of the incoming PAM-N data sets, is of fundamental importance to provide data rates per carrier equal or beyond 224 Gbit/s per wavelength and lane. Thus proposal focuses on various PAM-N, (N=4, 6, 8) modulation schemes to achieve this goal. Obviously, the optimum architectural choice results in a trade-off analysis between noise (SNR), CDR tracking bandwidth and jitter, PAM-N linearity (RLM) and signal bandwidth. In order to guarantee a robust PAM-4 / PAM-6 / PAM-8 CDR operation with superior bit-error rate (BER) and improved energy-efficiency per transmitted bit, the following scientific and technical challenges will be addressed: 1. New phase-locking algorithms suited for high-speed PAM-4 / PAM-6 / PAM-8 signals, eliminating the data dependent jitter 2. Ultra-low phase noise CDR and PLL 3. High-sensitivity wideband TIAs with adequate equalization 4. Highly linear wideband T&Hs and accurate ADCs 5. Traditional phase detectors (PD) such as the Alexander PD (APD), commonly used for NRZ data, lead to an unacceptable amount of data dependent jitter when applied to PAM-N signals, caused by the intermediate signal transitions with different phase delays. This proposal introduces a novel CDR approach, particularly tailored for PAM-N signals and overcoming the mentioned issues. The ultimate objective of this research proposal is to advance state-of-the-art optical Rx architectures by demonstrating a monolithically integrated high-speed low-jitter PAM-N CDR solution for future photonic transceivers. This technology not only enables significant robustness and bit-error rate improvements, but more importantly enables significant data rate up-scaling.

• DFG Programme: Research Grants