Synthesis of Approximated Hardware Accelerators with Monte-Carlo Tree Search (AxMCTS)

• Applicant: Professor Dr. Marco Platzner
• Subject Area: Computer Architecture, Embedded and Massively Parallel Systems
• Term: since 2023
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 516597319

The central idea of Approximate Computing (AxC) is to trade-off computational accuracy for a significant reduction in energy and/or execution time and/or chip area required to run an application. In the last years, AxC has strongly gained interest and approaches addressing various levels of the design hierarchy have been presented. At the level of digital components, the investigation of approximation techniques has already resulted in readily available libraries of approximated arithmetic circuits. When trying to design complete hardware accelerators out of such approximated components, we are faced with an extraordinarily huge design space. This makes an automated synthesis of hardware accelerators very challenging in terms of synthesis runtimes and quality of results. Our scientific hypothesis is that novel Monte-Carlo Tree Search (MCTS) techniques will lead to greatly improved efficiency for exploring the huge design space in approximate hardware accelerator synthesis. The AxMCTS project is original as-besides in our own initial work-MCTS has neither been applied to approximate hardware synthesis nor to hardware synthesis in general. However, in the last years MCTS has brought about great success in other domains, most prominently in playing games. By transferring MCTS techniques to AxC, we aim at creating synthesis methods and tools that deliver approximate accelerators with improved accuracy vs.~energy/performance trade-offs in much shorter runtime than possible today. The key research questions are: (i) Which MCTS principles and techniques can be transferred from domains where MCTS is highly successful, and where do we have to develop novel AxC-specific techniques to create a framework for approximate hardware accelerator synthesis? (ii) What are well-suited approaches and methods to improve the efficiency and runtime of the search process, for example by controlling the breadth of the search tree, by steering the search to the most promising regions of the search space, and by parallelizing the search. (iii) How to quantitatively evaluate the benefits and limitations of MCTS-based approximate hardware accelerator synthesis? Methodologically, we will study successful MCTS techniques, create an MCTS-based synthesis framework, and devise algorithmic methods for a more efficient search. In particular, we will apply deep neural networks for speeding up key steps in MCTS. Further, we will develop parallelized search techniques for execution on high-performance compute clusters. For the experimental evaluation we will conduct synthesis experiments targeting both FPGA backends and standard cell libraries, and the implementation will leverage and extend our previous open source framework CIRCA for approximate hardware synthesis.

• DFG Programme: Research Grants