Physical Design for Microfluidic Large-Scale Integration with Partitioning and Floorplanning

• Applicant: Dr.-Ing. Tsun-Ming Tseng
• Subject Area: Computer Architecture, Embedded and Massively Parallel Systems
• Term: since 2023
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 515003344

Microfluidic large-scale integration (mLSI) is an emerging platform for high-throughput cell-based applications, such as cell sorting, single-cell analysis, and DNA amplification. Analogous to electronic large-scale integration which integrates a large number of transistors on a tiny chip, an mLSI chip is integrated with hundreds to thousands of microchannels and micromechanical valves, and is able to execute complex assay sub-tasks, namely operations, in parallel in a precise manner. However, unlike electronic LSI which employs a top-down design approach with well-defined design rules and mature computer-aided design automation tools, mLSI development is still in its early phase. The design focus is usually on optimizing individual on-chip devices to construct the chip from bottom up. As a result, the quality of the design strongly relies on the knowledge and experiences of the designers, and the design procedure is time-consuming and error-prone even for bio-engineering experts. Thus, despite the advanced manufacturing technology and the rich set of microfluidic components, current microfluidic chips mostly either consist of only tens of on-chip devices, or have highly homogeneous structures that only support simple assay protocols. The gap between technology capabilities and design capabilities results in pressing demand for software synthesis tools, especially physical design tools that can efficiently synthesize and optimize the geometric layout of a chip. Over the past decade, physical design for mLSI has been modelled as a place & route problem to synthesize all geometric features of a chip in a single design step. However, an mLSI chip is usually composed of a variety of microfluidic components which differ in size, shape, functionality, connectivity and control complexity, etc. Thus, it is difficult for state-of-the-art place & route tools to handle the large design space in a single step. This proposal proposes to explore design partitioning and floorplanning for mLSI for the first time to solve the physical design problem in a hierarchical manner. With the proposed approach, we anticipate significant improvement in design quality and efficiency.

• DFG Programme: Research Grants