Learning-­based Efficient and Accurate Timing Analysis of Integrated Circuits

• Applicant: Professor Dr.-Ing. Ulf Schlichtmann, since 11/2024
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: since 2022
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 504518248

Since more than a decade, the clock frequency of integrated circuits (ICs) has been stagnant. A major source that prevents clock frequency from scaling is the rapidly increasing design and manufacturing complexity. On the one hand, nanometer devices in advanced technology nodes are affected more considerably by process and environmental variations. On the other hand, device scaling has enabled billions of transistors to be integrated into modern integrated circuits, which pose huge challenges in design closure. To analyze the circuit performance, nowadays timing analysis tools in the EDA (Electronic Design Automation) flow have adopted heuristic techniques to balance accuracy and efficiency. These heuristics, unfortunately, lead to a pessimistic underestimation of circuit performance and thus unnecessary timing margins, which often incur expensive and unnecessary design iterations. To address the explosion of IC design complexity, recently the EDA research community has started to turn to machine learning methods. However, timing analysis has not yet been covered sufficiently in this new research landscape. In this project, we plan to examine challenges in timing analysis of integrated circuits in advanced technology nodes and address them with learning-based methods to enhance the analysis accuracy. Specifically, we will process circuit information, e.g., path structures and gate locations, with techniques such as graph neural networks (GNNs) and convolutional neural networks (CNNs) to extract essential timing information. With such learning-based methods, the proposed framework can provide a good analysis accuracy efficiently to reduce the turnaround time of IC design. In addition, timing correlation across design stages will be established to enable valid early optimization. The proposed framework is technology-independent and learns timing information from training data, so that it is highly extensible and able to deal with new design challenges in future technology nodes.

• DFG Programme: Research Grants
• International Connection: China (Hong Kong)
• Co-Investigator: Professorin Dr.-Ing. Li Zhang
• Cooperation Partner: Professor Dr. Bei Yu
• Ehemaliger Antragsteller: Professor Dr.-Ing. Bing Li, until 11/2024