SMAUG: System-Level Modeling and Optimized Use of Disruptive Memory Technologies

• Applicant: Professor Dr.-Ing. Olaf Spinczyk
• Subject Area: Data Management, Data-Intensive Systems, Computer Science Methods in Business Informatics
• Term: since 2022
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 502565817

Besides the processing units, main memory is the most important resource in a computer system without which data processing would be de facto impossible. Various types of random access memory (RAM) have been used as main memory for several decades. RAM technology is under continuous development and, thus, got larger capacities, lower access latencies and higher data rates, but the basic properties of the main memory remained unchanged. It is traditionally homogeneous and byte-addressable. Memory contents are volatile, i.e. they are lost when the device is switched off. In addition, it is passive, i.e. it cannot process data independently. These typical properties are now firmly anchored in the expectations of software developers and manifest themselves in their products accordingly. We are now seeing a wave of innovations in memory technologies that defeat these assumptions. In this sense they are “disruptive” for the entire software industry and computer science. Examples of this are NVRAM (non-volatile and very special performance characteristics) and the first products that allow “Processing-in-Memory” (PIM) or “Near Memory Computing” (NMC) (main memory becomes active). In addition, there are technologies such as high-bandwidth memory (HBM) and extremely fast networks that allow “memory disaggregation” or direct memory access across computer boundaries (RDMA). Taken together, these innovations promise systems with higher processing power, lower energy consumption, more reliability and cost reductions. However, it is still largely unclear how complex platforms that integrate several of these technologies can be used in an optimized manner by future application and system software.This project is intended to remedy this. The first phase is about a methodology for creating formal models for the new hardware components, the topology of the overall system and the behavior of the software. The models should support flexible use cases, e.g. queries at runtime or compilation time, and therefore need a configurable level of detail. They should cover different non-functional properties and have a modular structure. Methods and tools should support all phases of the model life cycle, i.e. model generation, use and evolution. The practical suitability of the methodology is demonstrated by the exemplary modeling of the central hardware platform of the priority program. At the same time, the models can be used by other projects.The considered models are a crucial prerequisite for the development of optimized resource management strategies. With their help, control flows and data are to be placed in complex systems in such a way that bottlenecks and underutilization are avoided. This will initially be investigated only selectively and in the second phase in more depth.

• DFG Programme: Priority Programmes
• Subproject of: SPP 2377: Disruptive Main-Memory Technologies