Compact Modeling and Device Simulation of Terahertz InGaAs/InP Heterojunction Bipolar Transistors

• Applicant: Professor Dr.-Ing. Michael Schröter
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: since 2020
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 438512651

Heterojunction bipolar transistors (HBTs) possess the highest power handling capability and, through their extremely high transconductance, enable highest circuit speed. Indium-Phosphide (InP) based HBTs with an InGaAs base region are the first ones that have been demonstrated to have a power gain cut-off frequency above 1 Terahertz (THz). Such performance addresses the increasing interest in (sub-)mm-wave applications such as radar, imaging and chemicals detection for, e.g., transportation, health monitoring and security. In order to deploy such a high-speed HBT technology for designing circuits and systems, compact transistor models are required that capture measured transistor characteristics as accurately as possible over a wide bias, temperature, frequency and device geometry range. As shown in the proposal, not only is the accuracy of the existing typically used models inadequate but also is the variety of transistor sizes covered by those models very limited already for the previous technology generation. This prevents circuit optimization, e.g. for speed or energy efficiency, and thus prevents the full exploitation of a semiconductor technology. Furthermore, existing computationally efficient numerical device simulation does not work for InP HBTs, thus preventing valuable insights into the relevant physical effects. Finally, especially for nonlinear large-signal operation, validation of both compact and numerical models is limited to far below 100GHz by available and affordable measurement equipment. This project addresses all of the above mentioned issues. Major goals are: (i) Investigation of the electrical behavior and physical effects of the fastest InP HBT process technology. (ii) Development of a physics-based geometry scalable compact model and small-signal verification up to 325 GHz. (iii) Development of a computationally efficient two-valley drift-diffusion solver. (iv) Applying of a novel on-chip measurement approach for large-signal transistor characterization and model verification up to several 100GHz.

• DFG Programme: Research Grants