Design and Architecture for Racetrack based Hybrid Memory Systems

• Applicant: Dr.-Ing. Fazal Hameed
• Subject Area: Computer Architecture, Embedded and Massively Parallel Systems
• Term: from 2020 to 2022
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 437232907

The increasing memory capacity requirements along with the quest for high performance and low energy have made the memory system design extremely difficult. The conventional DRAM memory has reached its fundamental and physical limitation that likely prevents it from growing in capacity. The recently proposed spin-orbitronics based RaceTrack Memory (RTM) is a novel memory-storage technology that accesses and stores binary data on nanoscale magnetic wires allowing exorbitant density as well as the ability to overcome the technology scaling limitations. Despite key technological advancements, the access latency and energy consumption of RTM is highly influenced by the number of shift operations. These operations are required to move bits to the right positions in the racetracks. To enable adoption of RTM, this proposal envisions a hybrid memory system by combining RTM with DRAM and Spin Transfer Torque (STT) memories at different levels in the memory hierarchy.The hybrid memory system not only offers huge opportunities but also presents daunting challenges to handle large set of data. These systems need to adapt to the application’s diverse memory access patterns, and at the same time they need to avoid the inherent limitations of individual memories constituting them. This requires a radical shift in the memory system design and a need to revisit data management strategies at hardware and operating system level.The overall goal of this proposal is to lay the foundation for highly efficient data management on hybrid memory system. We will achieve this goal by enabling hardware and operating system joint optimizations so that applications can exploit the inherent potential of the envisioned hybrid memory system despite the extra complexity brought in by heterogeneity. Concretely, we will work on design of relatively newer RTM and its adaptation, on RTM controller design, on data classification and analysis, on hierarchy adaptation, and on system-wide data management. We will follow a co-design methodology as a way to bridge the gap between hardware and operating system layers that is greatly enlarged by the high disruption potential of hybrid memory system. On the hardware side, we will deeply investigate the architecture of the RTM to enable its efficient integration with other memories. By leveraging hardware performance monitors and intelligent controllers, we will fully describe different properties of application data and memory behavior. This will guide the hardware and the operating system (OS) to take appropriate data mapping, data remapping, RTM adaptation, and hierarchy adaptation decisions. We envisage HW-OS collaborative mechanisms to continuously adapt to the change in application data behavior and system load. This project will thus contribute to mitigate the gap between the hardware and operating system layers, enabling efficient integration of relative newer RTM with well-established memory technologies.

• DFG Programme: Research Fellowships
• International Connection: Pakistan
• Host: Professor Khurram Khurshid, Ph.D.