Ensuring Robustness in Low-Power Asynchronous Circuits - ENROL
Final Report Abstract
The main goal of ENROL project was to ensure robustness in efficient asynchronous circuits, systematically classifying and extending transient-fault mitigation techniques to circuit and architecture level with a broad coverage. The ENROL approach was bottom-up, starting with a comprehensive fault modeling, up to a quantitative simulative assessment of their respective effectiveness, thus allowing comparisons and further optimization. The project concepts went beyond the simplified and today unrealistic limits of single-event transients. The ENROL approach proposed Asynchronous Full Error Detection and Correction (AFEDC) architecture, that has shown excellent fault tolerance features, followed by improved metastability protection, comparable performances, and reduced power consumption and area complexity compared to the corresponding synchronous solutions. Moreover, multi-bit errors were addressed in ENROL both at the physical i.e. spatial level as well as the architectural level. The complete development process have been addressed as well, proposing the designflow that enables implementation of corresponding fault tolerant asynchronous circuits. The achieved results could be the basis for more efficient and robust asynchronous bundled data circuits. The ENROL project has achieved its main targets and it is considered as very successful and baseline for the further research in the domain of reliable asynchronous logic design.
Publications
- “Delay lines test method for the Blade Template,” Fresh Ideas in 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 1–2, 2019
F. A. Kuentzer, L. R. Juracy, M. T. Moreira, and A. M. Amory
(See online at https://doi.org/10.48550/arXiv.1905.11218) - “Soft Error Detection and Correction Architecture for Asynchronous Bundled Data Designs,” Fresh Ideas in 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 1–2, 2019
F. A. Kuentzer and M. Krstic
- "Test Oriented Design and Layout Generation of an Asynchronous Controller for the Blade Template," in Proc. 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 86–93, 2020
F. A. Kuentzer, L. R. Juracy, M. T. Moreira and A. M. Amory
(See online at https://doi.org/10.1109/ASYNC49171.2020.00021) - “Radiation Hardened Click Controllers for Soft Error Resilient Asynchronous Architectures,” in Proc. 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 78–85, 2020
F. A. Kuentzer, M. Herrera, O. Schrape, P. A. Beerel, and M. Krstic
(See online at https://doi.org/10.1109/ASYNC49171.2020.00020) - “Soft Error Detection and Correction Architecture for Asynchronous Bundled Data Designs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 12, pp. 4883-4894, 2020
F. A. Kuentzer and M. Krstic
(See online at https://doi.org/10.1109/TCSI.2020.2998911) - “Addressing Multi-bit Transient Faults in Asynchronous RH-Click Controllers,” Fresh Ideas in 27th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 1–2, 2021
F. A. Kuentzer and M. Krstic
- “Assessing AFEDC Architecture’s Robustness to Timing Faults,” in 33. GI/GMM/ITG-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2021), pp. 1–2, 2021
F. A. Kuentzer and M. Krstic
- “Testing The Blade Resilient Asynchronous Template” Analog Integrated Circuits and Signal Processing, vol. 106, no. 1, pp. 219–234, 2021
F. A. Kuentzer, L. R. Juracy, M. T. Moreira, and A. M. Amory
(See online at https://doi.org/10.1007/s10470-020-01651-8)
