Hardware/Software Cross-Layer Fault Analysis for Safe Embedded System Design
Security and Dependability, Operating-, Communication- and Distributed Systems
Final Report Abstract
Throughout today’s industrial world Embedded System technology is taking over more and more tasks in safety-and and security-critical applications. Autonomous driving is a prominent example. As a result, the requirement of functional safety has become a key concern and, not rarely, defines the “economic operating point” of a new technology. At the same time, as a result of new microelectronic fabrication technologies, new hardware devices are emerging which suffer from an intrinsically higher susceptibility to faults than previous devices. This leads to a substantially lower degree of reliability and demands further improvements of methods for error protection. However, any attempt to cover all errors for all theoretically possible scenarios that a system might be used in can easily lead to excessive costs. There is consensus within the testing community that new application-dependent approaches are needed to meet these challenges. This means that strategies for test and error resilience must target only those errors that can really have an effect in the applications in which the hardware is actually used. These applications are defined by the software. The reported project has investigated and developed a HW/SW cross-layer approach to assess the effect of hardware faults at the software level. Methods have been researched that allow for a formal analysis tracing the propagation of hardware faults when executing the system’s software. Our research provides techniques to identify hardware faults that do not have any effect on the software or on selected, possibly safety-critical, software components. Moreover, the developed approach allows us to classify faults with respect to their fault effects. For example, faults can be identified that may affect the data of a program but it is guaranteed that they do not change its control flow. The proposed approach does not only give hints on what faults are particularly critical. In contrast to previous simulation-based approaches it can certify that certain faults do not affect the system behavior at all, or that the effect is limited to certain sub-functions. This information is highly valuable when evaluating the safety of a system and when taking possible measures for fault protection. During the reported project period, hardware security gained great importance. Therefore, we also explored security issues at the HW/SW interface laying the foundation for new approaches to formal security analysis and for improving the resilience of system security at the presence of fault attacks. Extending significantly over the originally proposed concepts for cross-layer safety analysis, we combined our low-level formal analysis of firmware with Abstract Interpretation. We created a framework for formal cross-layer safety analysis based on sound abstractions that formally links low-level hardware faults across the hardware-dependent software layer to high-level application software. We demonstrated the significance and scalability of our approach for an embedded system running software with more than 100,000 lines of C-code.
Publications
- “A HW/SW Cross-Layer Approach for Determining Application-Redundant Hardware Faults in Embedded Systems,” Journal of Electronic Testing (JETTA), vol. 33, pp. 77 – 92, Springer, 2017
C. Bartsch, C. Villarraga, D. Stoffel, and W. Kunz
(See online at https://doi.org/10.1007/s10836-017-5643-3) - “Efficient Binary-Level Coverage Analysis,” in ACM Joint European Software Engineering Conference and Symposium on the Foundations of Software Engineering - ESEC/FSE’20, November 2020
M. A. Ben Khadra, D. Stoffel, and W. Kunz
(See online at https://doi.org/10.1145/3368089.3409694) - “Compositional Fault Propagation Analysis in Embedded Systems Using Abstract Interpretation”, IEEE International Test Conference (ITC), October 2021
Daniel Kästner, Stephan Wilhelm, Christian Bartsch, Dominik Stoffel and Wolfgang Kunz
(See online at https://doi.org/10.1109/ITC50571.2021.00057) - “Combining Fault Effect Analysis and Fault Propagation Analysis to Determine Source-Level Effects of Hardware Faults”, Embedded World Conference and Exhibition, June 2022
Christian Bartsch, Stephan Wilhelm, Daniel Kästner, Dominik Stoffel and Wolfgang Kunz
- “Generation of Formal CPU Profiles for Embedded Systems”, 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Patras, Greece, 2022
Stian Sørensen, Christian Bartsch, Dominik Stoffel and Wolfgang Kunz
(See online at https://doi.org/10.1109/VLSI-SoC54400.2022.9939572)
