Hardware/Software Cross-Layer Fault Analysis for Safe Embedded System Design

• Applicant: Professor Dr.-Ing. Wolfgang Kunz
• Subject Area: Computer Architecture, Embedded and Massively Parallel Systems ; Security and Dependability, Operating-, Communication- and Distributed Systems
• Term: from 2017 to 2023
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 360597144

Throughout today's industrial world Embedded System technology is taking over more and more tasks in safety-critical applications. Autonomous driving is a prominent example. As a result, the requirement of functional safety has become a key concern and, not rarely, defines the economic operating point of a new technology. At the same time, as a result of new microelectronic fabrication technologies, new hardware devices are emerging which suffer from an intrinsically higher susceptibility to faults than previous devices. This leads to a substantially lower degree of reliability and demands further improvements of methods for error protection. However, any attempt to cover all errors for all theoretically possible scenarios that a system might be used in can easily lead to excessive costs. There is consensus within the testing community that new application-dependent approaches are needed to meet these challenges. This means that strategies for test and error resilience must target only those errors that can really have an effect in the applications in which the hardware is actually used. These applications are defined by the software. The proposed project pursues the goal of developing a HW/SW cross-layer approach to assess the effect of hardware faults at the software level. The focus of the proposed analysis will lie on low-level software. Methods will be researched that allow for a formal analysis tracing the propagation of hardware faults when executing the system's software. A particular goal of our research is to provide techniques and a tool to identify hardware faults that do not have any effect on the software or on selected, possibly safety-critical, software components. Moreover, the envisioned approach will allow us to classify faults with respect to their fault effects. For example, faults can be identified that may affect the data of a program but it is guaranteed that they do not change its control flow.The proposed approach does not only give hints on what faults are particularly critical. In contrast to previous simulation-based approaches it can certify that certain faults do not affect the system behavior at all, or that the effect is limited to certain sub-functions. This information is highly valuable when evaluating the safety of a system and when taking possible measures for fault protection. The project will give a first demonstration for the usefulness of the proposed analysis by applying it to design measures that improve the fault resilience of the system.

• DFG Programme: Research Grants