Design of Hardware Transactional Memory for Usage in Embedded Systems
Image and Language Processing, Computer Graphics and Visualisation, Human Computer Interaction, Ubiquitous and Wearable Computing
Final Report Abstract
Hardware transactional memory is a hardware mechanism that can improve the runtime of applications on multi-cores through optimistic synchronization and simplifies their development. This project investigated the use of hardware transactional memory on embedded systems. Several barriers were identified during this investigation. Traditional hardware transactional memories are often subject to size limitations. This can lead to problems if unexpectedly large amounts of data are generated. For example, an autonomous car needs to be able to detect all pedestrians in its vicinity, even if an unexpectedly large group crosses the road. We have implemented a solution in the form of a transaction management unit, which can handle such extreme cases. We also provide prioritization, through which it is possible to prioritize important tasks, such as controlling the brakes, over irrelevant ones, such as the radio. The transaction management unit can also prevent livelocks, in which transactions repeatedly abort each other, causing the system to freeze. In addition, a novel mechanism has been developed that allows the system to tolerate faults that may arise, for example, from radiation. This fault tolerance mechanism can also be used in particular on heterogeneous multi-cores, which consist of powerful and energy-efficient cores. This makes it particularly well suited for use in modern embedded systems, such as those used in autonomous cars, which require high computing power while being powered by a battery. Moreover, in the event of a fault, our approach can return to a fault-free state and continue execution from there. Many classical approaches can only stop execution in the event of a fault and remain in a safe state. Ultimately, the user must then perform a restart. Depending on the requirements of the embedded system, the use of hardware transactional memory may be appropriate. Our transaction management unit simplifies development. Our fault tolerance approach enables the use of such systems even for safety-critical use cases. The overall system can provide high performance with low power requirements.
Publications
- „Redundant Execution on Heterogeneous Multi-cores Utilizing Transactional Memory“. In: International Conference on Architecture of Computing Systems (ARCS). Springer. 2018, S. 155–167
Rico Amslinger, Sebastian Weis, Christian Piatka, Florian Haas und Theo Ungerer
(See online at https://doi.org/10.1007/978-3-319-77610-1_12) - „Hardware Multiversioning for Fail-Operational Multithreaded Applications“. In: 32nd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). IEEE. 2020, S. 20–27
Rico Amslinger, Christian Piatka, Florian Haas, Sebastian Weis, Theo Ungerer und Sebastian Altmeyer
(See online at https://doi.org/10.1109/SBAC-PAD49847.2020.00014) - „Investigating Transactional Memory for High Performance Embedded Systems“. In: International Conference on Architecture of Computing Systems (ARCS). Springer. 2020, S. 97–108
Christian Piatka, Rico Amslinger, Florian Haas, Sebastian Weis, Sebastian Altmeyer und Theo Ungerer
(See online at https://doi.org/10.1007/978-3-030-52794-5_8) - „Loosely-Coupled Fail-Operational Execution on Embedded Heterogeneous Multi-Cores“. Diss. University of Augsburg, 2021
Rico Amslinger
