Design-for-Test and Design-for-Reliability for Low Power STT-MRAM

• Applicant: Professor Mehdi B. Tahoori, Ph.D.
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering ; Computer Architecture, Embedded and Massively Parallel Systems
• Term: from 2015 to 2022
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 286543208

With the continuation of Moore s law, the microelectronics industry faces major challenges related to power dissipation and energy consumption in the next years. Therefore, it is a fundamental challenge and necessity to stop this trend, particularly for emerging low-power application domains such as the (IoT). A promising approach to achieve this is to add non-volatility as a new feature of memories, which would immediately minimize static power as well as paving the way towards normally-off/instant-on computing. The use of emerging spin-based non-volatile memory devices, aka Magnetic Random Access Memory (MRAM), in the memory hierarchy of computing systems provides a huge opportunity for low-power. However, the MRAM technology is also facing various fundamental research and scientific challenges that have to be addressed to make it a viable solution for low-power computing platforms, such as IoT. These issues are related to manufacturing yield, test, and reliability of this emerging technology. Therefore, the objective of this research project is to comprehensively model the various faults at different abstraction levels to perform a reliability-aware design space exploration for MRAM. Then, we will investigate Design-for-Test (DfT) and Design-for-Reliability (DfR) to improve test quality (e.g. coverage) and reliability of MRAM-based systems.

• DFG Programme: Research Grants