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NaSCA: Nano-Scale Side-Channel Analysis - Physical Security for Next-Generation CMOS ICs

Subject Area Computer Architecture, Embedded and Massively Parallel Systems
Term from 2016 to 2021
Project identifier Deutsche Forschungsgemeinschaft (DFG) - Project number 271752544
 
Currently we are being surrounded by an ever-growing number of cyber-physical systems e.g., electronic toll collection, traffic management, electronic payments, smart homes etc. Although this offers many benefits, the embedded security-enabled devices are in control of legitimate users, who can play the role of an adversary. It enables serious risks with respect to system security, not only due to the flaws of crypto algorithms. Also, the implementation attacks, as serious threats for pervasive applications, can turn a theoretically-robust system into a completely-broken setup. As demonstrated by numerous side-channel analysis (SCA) attacks, securing ubiquitous systems is a must as well as a non-trivial task. Interestingly, the SCA community offers a large toolbox of advanced countermeasures for protecting the crypto devices against such physical attacks. The power analysis countermeasures have been designed based on the principle of dynamic power consumption. However, by fast technology shrinking static power consumption of nano-scale CMOS circuits is becoming a major concern. Hence, the known countermeasures have serious shortcomings when static power consumption is considered by an SCA adversary. In the near future the cryptographic devices, equipped with theoretically-sound countermeasures, will fail to provide the desired level of protection as their security is provable excluding the concept of static power. Indeed, the result of our preliminary study in this area, where we examined the SCA vulnerability of FPGA platforms through static power, supports this statement. Nevertheless, it would be a great benefit to develop protection solutions considering both dynamic and static power. We believe that this is possible, at least to a certain extent, by carefully re-designing, extending, and composing the known countermeasures. In this project we will investigate SCA through static power for FPGA and ASIC platforms. We will analyze the efficiency of the known countermeasures to protect crypto devices (e.g., an AES coprocessor) against static power analysis attacks. Based on this, countermeasures will be (re-)designed to match the certain requirements resulting in more robust schemes with enhanced functionality. We will develop dedicated and provably-secure countermeasures (for FPGA and ASIC platforms) based on the result of our practical analyses. The fabricated ASIC samples and the FPGA modules will be practically evaluated to ensure the robustness of our developed countermeasures. Hence, an interdisciplinary effort based on applied cryptography and cryptographic engineering is required to cope with these challenges.In contrast to our approach, previous works usually deal with solely dynamic power side channel, use heuristic physical security techniques or basic obfuscation schemes, and lack sound proof to prove the security. In fact, resistance against SCA attacks through static power has barely been considered by the SCA community.
DFG Programme Research Grants
 
 

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