Analog circuits with time varying parameters caused by device aging and gate currents: modelling of impact on circuit behaviour; assessment and development of countermeasures.
Final Report Abstract
Degradation in analog circuits depends on circuit topology and time dependent node voltages. Therefore, we have developed a new simulation model for dynamic and long-term NBTI degradation. It is based on capture and emission statistics of charge traps and uses groups of traps to shorten simulation time for use in circuit analysis. That way transient simulations of analog-sized transistors for reliability examinations are feasible. The proposed model covers DC-stress, AC-stress and recovery behavior depending on stress voltage, temperature and time. To demonstrate the effects of NBTI recovery on analog circuits, we analyzed a comparator in switchedcapacitor technology with auto-zeroing technique. Short stress pulses and subsequent recovery can cause switching threshold instabilities and erroneous circuit behavior despite the implemented auto-zeroing. With help of the proposed NBTI model, which covers recovery in every simulation step, one can reveal that even short-term threshold changes can lead to failures in analog circuits like comparators or converters. This shows that dynamic simulation of NBTI recovery is required to identify potential sources of error in analog circuits. The proposed NBTI model is not limited to analog circuits. Also, other circuit topologies can be analyzed to identify circuits which are prone to NBTI and specially to fast changing threshold voltage changes. This includes all circuits where metastable states may occur, such as converters, SRAM circuits, oscillator circuits and flip-flops. Further we developed a concept for measuring changes in the threshold Voltage Vth in the nanosecond regime, designed and layouted a test chip with our industry partner Infineon Technologies and setup a proof-of-concept measurement environment and routine. Investigation of short-term reliability in analog circuits is a complex issue since it must consider many influences. Among others, the severeness of short-term NBTI effects depends on the circuit topology, time dependent node voltages and the specific circuit use case. Due to this complexity, this thesis could give only a short insight into the possible consequences of shortterm stress and relaxation. Therefore, future work on different circuit topologies will be definitely necessary to collect a well-founded knowledge on short-term reliability in analog and mixed-signal circuits. Besides NBTI, future work on short-term reliability in high-κ metal gate technologies will also have to consider positive bias temperature instability (PBTI) in nMOS transistors. Similarly, to NBTI, PBTI degrades the threshold voltage of nMOS transistors. As PBTI will introduce additional parameter shifts in analog circuits, the effects caused by short-term stress and relaxation are expected to play a major role for future CMOS nodes. Research has shown that PBTI can be modeled analogously to NBTI based on charge trapping and detrapping, i.e. the analytic model for NBTI presented in this thesis is applicable to PBTI as well.
Publications
- "Modeling of NBTI-recovery effects in analog CMOS circuits," 2013 IEEE International Reliability Physics Symposium (IRPS), Anaheim, CA, 2013, pp. 2A.4.1- 2A.4.4
C. Yilmaz, L. Heiß, C. Werner and D. Schmitt-Landsiedel
(See online at https://dx.doi.org/10.1109/IRPS.2013.6531944) - "Short Term NBTI Degradation in Switched-Capacitor Circuits", ANALOG 2013
Leonhard Heiß, Cenk Yilmaz, Christoph Werner, Doris Schmitt-Landsiedel
- "In situ measurement of aging-induced performance degradation in digital circuits," 2016 21th IEEE European Test Symposium (ETS), Amsterdam, 2016, pp. 1-2
N. P. Aryan, C. Funke, J. Barsgfrede, C. Yilmaz, D. Schmitt-Landsiedel and G. Georgakos
(See online at https://dx.doi.org/10.1109/ETS.2016.7519285)
