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Projekt
MixedCoreSoC - A Highly Dependable Self-Adaptive Mixed-Signal Multi-Core System-on-Chip
Antragsteller
Professor Dr. Uwe Brinkschulte; Professor Dr.-Ing. Lars Hedrich
Fachliche Zuordnung
Rechnerarchitektur, eingebettete und massiv parallele Systeme
Förderung
Förderung von 2010 bis 2016
Projektkennung
Deutsche Forschungsgemeinschaft (DFG) - Projektnummer 181384236
Future embedded Systems on Chip (SoC) will have to meet several new requirements given by upcoming applications and hardware platforms: High dependability in the presence of unreliable hardware will be a key feature due to degrading process reliability and device ageing caused by increasing integration density. Selfadaptation is necessary to adapt to a changing hardware platform and changing environment. The increasing importance of analog parts requires mixed-signal processing. Real-time requirements in combination with self-adaptation and unreliable hardware are another design challenge.Therefore, we proposed the MixedCoreSoC architecture being composed of a generalized core and task concept in combination with an artificial hormone system (AHS) to meet these requirements. In the first project phase we developed the key concepts of the architecture and validated these concepts by simulation. In the second project phase requested in this proposal, we focus on four major issues:First, we want to complete the system design by adding reliable hormone-controlled interface and inter-core communication networks. Furthermore, failures in the artificial hormone system will be considered. These aspects have been intentionally left out in the first project phase. A special focus is also set on mixed signal task migration.Second, predictable dependability is envisioned as it is a key feature for embedded real-time applications. So a detailed analysis of the dependability and predictability parameters will be conducted to quantify the dependability gain reached and to allow guarantees on availability and worst-case delay as a function of failure rates. Furthermore, statistic failure measures like MTTF and yield increase will be derived. The trade-off between reliability, real-time properties and energy consumption is another aspect to be investigated.Third, a design methodology for developing applications using the MixedCoreSoC architecture will be established. Due to the variety of the design space, support for a user in selecting vital design parameters of the MixedCoreSoC architecture is essential. Therefore, a design flow to synthesize a concrete dependable system with desired properties on a given technology is envisioned. A toolkit for an iterative optimization of the design decisions would also be helpful.Fourth, the step from pure simulation to an extended evaluation based on a prototype and a real-world application scenario is provided to confirm and deepen the achieved results and to address aspects hard to cover in simulation like e.g. real-time behavior with respect to peripheral sensor/actor components or energy related issues. Therefore, a prototypic implementation of the MixedCoreSoC architecture in combination with a real demonstrator application is intended. Based on this, a detailed evaluation of performance, dependability, predictability and costs will be performed.The proposed project fits the frame of the priority programme 1500, because it substantially contributes to increase the dependability of embedded systems by an innovative hardware architecture using a biologically inspired operation principle and a corresponding design method.
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