Experimental and theoretical investigations of mono- and bilayer graphene nanoribbon band-to-band tunneling field-effect transistors
Final Report Abstract
In recent years, the power consumption of highly integrated circuits (ICs) has become a major obstacle to further increase the complexity and performance of future ICs. The reason for this power crisis is the operating principle of conventional field-effect transistor devices that need a minimum operating voltage for proper performance. Therefore, so-called steep slope transistors that exhibit a superior switching behavior and thus the ability to further decrease the operating voltage and hence power, are currently investigated intensively worldwide. In particular, band-to-band tunneling FETs (TFETs) are considered as the most promising device architecture. However, in TFETs current is modulated by gate-controlled band-to-band tunneling and it has been shown that very steep source-channel p-n-junctions with a large band-to-band tunneling probability are required in order to realize TFETs with a switching behavior superior to conventional MOSFET. To this end, a number of performance boosters have been identified with the most effective ones are an ultrathin gate dielectric and an ultrathin channel layer. The latter is the reason why 2D materials such as graphene and transition metal dichalcogenides have been subject to investigations in the framework of TFETs. Appropriate doping of such materials is key to the realization of TFETs. But doping is a rather delicate task and very difficult in these materials. The current project, therefore, investigated the use of electrostatic doping, i.e. using gates in source, channel and drain. The major benefit of this is that the screening of the gate impact on the source contact can be disentangled from the amount of doping in the source region. This is very important since a good screening with high doping density may yield a TFET device that shows almost the same switching behavior as a conventional MOSFET. Socalled buried triple-gate substrates (BTGs) have been developed and fabricated where three individually addressable gates were integrated in close proximity. To avoid a substantial gate-underlap, anisotropic etching of silicon and a modified local-oxidation-of-silicon process were employed. Furthermore, the BTGs provide a smooth surface and can be adjusted to allow an easy identification of the 2D materials with optical microscopy. Applying appropriate gate voltages, the BTGs allow to reconfigure devices and operate them as conventional ntype, p-type and TFET transistors. Experimental devices based on graphene nanoribbons and on WSe2 have been fabricated and investigated. In both cases, transistors with reconfigurable source and drain electrodes were realized. In the case of WSe2, switching from n-type to p-type devices with a ratio between on- and off-current of several orders of magnitude on the same flake were demonstrated. In addition, a TFET device configuration was also obtained. However, the switching behavior is still worse than in the conventional FETs. The reason for this is the processing of the BTGs that led to a gate-underlap. Improved buried-triple-gate substrates have been fabricated that are currently being used to realize improved TFETs based on various TMDs and other 2D materials.
Publications
- „Chemical-Mechanical Planarization of Aluminium Damascene Structures“, ICPT 2012, 1-6 (2012)
U. Künzelmann, M.R. Müller, K.T. Kallis, F. Schütte, S. Menzel, S. Engels, J. Fong, C. Lin, J. Dysard, J.W. Bartha and J. Knoch
- „Optimizing the identification of mono- and bilayer graphene on multilayer substrates”, Appl. Optics 51, 385-389 (2012)
C. Kontis, M.R. Müller, C. Küchenmeister, K.T. Kallis and J. Knoch
(See online at https://doi.org/10.1364/AO.51.000385) - “Gate-controlled doping in carbon-based FETs”, 2013 VLSI-SoC, 162-167 (2013)
J. Knoch, T. Grap and M. Müller
- “Buried triple-gate structures for advanced fieldeffect transistor devices”, Microelectron. Engin. 119, 95-99 (2014)
M.R. Müller, A. Gumprich, F. Schütte, K. Kallis, U. Künzelmann, S. Engels, C. Stampfer, N. Wilck and J. Knoch
(See online at https://doi.org/10.1016/j.mee.2014.02.001) - „Electrostatic Doping - Controlling the properties of carbon-based FETs with gates“, IEEE Trans. Nanotechnol. 13, 1044-1052 (2014)
J. Knoch and M. Müller
(See online at https://doi.org/10.1109/TNANO.2014.2323436) - „Tachkling hillocks growth after aluminum CMP“, ICPT 2014, 129-132 (2014)
M.R. Müller, K.T. Kallis, S. Menzel, U. Künzelmann, I. Petrov and J. Knoch
(See online at https://doi.org/10.1109/ICPT.2014.7017263) - „Visibility of two-dimensional layered materials on various substrates”, J. Appl. Phys. 118, 145305 (2015)
M. R. Müller, A. Gumprich, E. Ecik, K. T. Kallis, F. Winkler, B. Kardynal, I. Petrov, U. Kunze, and J. Knoch
(See online at https://doi.org/10.1063/1.4930574) - „Gate-Controlled WSe2 Transistors Using a Buried Triple-Gate Structure“. Nanoscale Research Letters, December 2016, 11:512
M.R. Müller, R. Salazar, S. Fathipour, H. Xu, K. Kallis, U. Künzelmann, A. Seabaugh, J. Appenzeller and J. Knoch
(See online at https://doi.org/10.1186/s11671-016-1728-7) - „Transistion Metal Dichalcogenide Schottky Barrier Transistors – A Device Analysis and Material Comparison“, p. 207-240, chapter 8 in 2D Materials for Nanoelectronics, Ed. M. Houssa, A. Dimoulas and A. Molle, CRC Press, 2016
J. Appenzeller, F. Zhang, S. Das and J. Knoch
